Wei Song's web space


    Journal and Conference Papers


    Secure Computer Architecture

  1. Wei Song, Da Xie, Zihan Xue, and Peng Liu. A parallel tag cache for hardware managed tagged memory in multicore processors. IEEE Transactions on Computers, vol. 73, no. 11, 2488-2503, 2024. (CCF-A) [DOI, PDF]
  2. Wei Song, Zihan Xue, Jinchi Han, Zhenzhen Li, and Peng Liu. Randomizing set-associative caches against conflict-based cache side-channel attacks. IEEE Transactions on Computers, vol. 73, no. 4, pp. 1019-1033, 2024. (CCF-A) [DOI, PDF]
  3. Zhenzhen Li, Xue Zihan, and Wei Song. Feasibility analysis and performance optimization of the conflict test algorithms for searching eviction sets. In Proceedings of the International Conference on Information Security and Cryptology (ICISC), Seoul, South Korea, pp. 214-232, November 2023. [DOI, PDF]
  4. 邢明杰, 宋威, 张科, 易秋萍. RISC-V技术及生态专题前言. 计算机系统应用, 2023, 32(11): 1–2. [WEB]
  5. 解达, 欧阳慈俨, 宋威. RISC-V架构硬件辅助用户态内存安全防御方案概览. 计算机系统应用, 2022, 32(11): 11–20.
    (Da Xie, Ciyan Ouyang, and Wei Song. A summary of hardware-assisted user-mode memory safety defenses on RISC-V architecture. Computer Systems & Applications, vol. 32, no. 11, pp. 11–20, 2023) [WEB]
  6. Zihan Xue, Jinchi Han, and Wei Song. CTPP: A fast and stealth algorithm for searching eviction sets on Intel processors. In Proceedings of the International Symposium on Research in Attacks, Intrusions, and Defenses (RAID), pp. 151–163, Hongkong, China, October 2023. (CCF-B) [DOI, PDF]
  7. Wei He, Zhi Zhang, Yueqiang Cheng, Wenhao Wang, Wei Song, Yansong Gao, Qifei Zhang, Kang Li, Dongxi Liu, and Surya Nepal. WhistleBlower: A system-level empirical study on RowHammer. IEEE Transactions on Computers, accepted, 2023. (CCF-A) [DOI]
  8. 武延军, 宋威, 张科, 邢明杰. RISC-V技术及生态专题前言. 计算机系统应用, 2022, 31(9): 1–2. [WEB]
  9. 沈思豪, 解达, 宋威. 跨平台内存安全测试集设计. 计算机系统应用, 2022, 31(9): 39–49.
    (Sihao Shen, Da Xie, and Wei Song. Design of cross-platform memory safety test suite. Computer Systems & Applications, vol. 31, no. 9, pp. 39–49, 2022) [WEB]
  10. Sihao Shen, Zhenzhen Li, and Wei Song. Methods of extracting parameters of the processor caches. In Proceedings of the International Workshop on Security (IWSEC), pp. 47–65, September 2022. [DOI, PDF]
  11. Wei Song, Jiameng Ying, Sihao Shen, Boya Li, Hao Ma, and Peng Liu. A comprehensive and cross-platform test suite for memory safety -- Towards an open framework for testing processor hardware supported security extensions. arXiv:2111.14072, November 2021. (non-refereed but still important) [ArXiv, PDF]
  12. 薛子涵, 解达, 宋威. 基于RISC-V的新型硬件性能计数器. 计算机系统应用, November 2021, 30(11): 3–10.
    (Zihan Xue, Da Xie, and Wei Song. Hardware performance counter based on RISC-V. Computer Systems & Applications, vol. 30, no. 11, pp. 3–10, 2021) [WEB]
  13. Wei Song, Boya Li, Zihan Xue, Zhenzhen Li, Wenhao Wang, and Peng Liu. Randomized last level caches are still vulnerable to cache side channel attacks! But we can fix it. In Proceedings of the IEEE Symposium on Security and Privacy (S&P), Online, pp. 955–969, May 2021. (CCF-A) [DOI, PDF, ArXiv]
  14. 李小馨, 宋威, 付霄飞, 赵路坦, 李沛南, 侯锐, 孟丹. 缓存布局重映射：缓存侧信道攻击防御研究. In CCF全国计算机体系结构学术年会, August 2020.
  15. Wei Song and Peng Liu. Dynamically finding minimal eviction sets can be quicker than you think for side-channel attacks against the LLC. In Proceedings of the International Symposium on Research in Attacks, Intrusions and Defenses (RAID), Beijing, China, pp. 427–442, September 2019. (CCF-B) [WEB, PDF]
  16. Jun Zhang, Rui Hou, Wei Song, Sally A. McKee, Zhen Jia, Chen Zheng, Mingyu Chen, Lixin Zhang, and Dan Meng. RAGuard: An efficient and user-transparent hardware mechanism against ROP attacks. ACM Transactions on Architecture and Code Optimization (TACO), vol. 15, no. 4, pp. 50:1-50:21, 2019. (CCF-A) [DOI, PDF]
  17. Jianping Zhu, Wei Song, Ziyuan Zhu, Jiameng Ying, Boya Li, Bibo Tu, Gang Shi, Rui Hou, and Dan Meng. CPU security benchmark. In Proceedings of the 1st Workshop on Security-Oriented Designs of Computer Architectures and Processors, Toronto, ON, Canada, pp. 8–14, 2018. [DOI, PDF]
  18. Jun Zhang, Rui Hou, Wei Song, Zhiyuan Zhan, Boyan Zhao, Mingyu Chen, and Dan Meng. Stateful forward-edge CFI enforcement with Intel MPX. In CCF TCArch Bienneial Conference on Advanced Computer Architecture (ACA), Yingko, Liaoning, China, August 2018. [DOI, PDF]

    19. Asynchronous Network-on-Chip, VLSI

  19. Guangda Zhang, Wei Song, Jim Garside, Javier Navaridas, and Zhiying Wang. Handling physical-layer deadlock caused by permanent faults in quasi-delay-insensitive network-on-chip. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 25, no. 11, pp. 3152–3165, 2017. (CCF-B) [DOI, PDF]
  20. Guangda Zhang, Jim Garside, Wei Song, Javier Navaridas, and Zhiying Wang. Deadlock recovery in asynchronous networks on chip in the presence of transient faults. In Proceedings of International Symposium on Asynchronous Circuits and Systems (ASYNC), Silicon Valley, California, US, pp. 100–107, May 2015. [DOI, PDF]
  21. Guangda Zhang, Wei Song, Jim Garside, Javier Navaridas, and Zhiying Wang. Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes. Microprocessors and Microsystems, vol. 38, no. 8, pp. 826–842, 2014. (CCF-C) [DOI, PDF]
  22. Guangda Zhang, Wei Song, Jim Garside, Javier Navaridas, and Zhiying Wang. An asynchronous SDM network-on-chip tolerating permanent faults. In Proceedings of International Symposium on Asynchronous Circuits and Systems (ASYNC), Potsdam, Germany, pp. 9–16, May 2014. [DOI, PDF]
  23. Wei Song, Guangda Zhang, and Jim Garside. On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip. In Proceedings of International Conference of the Great Lakes Symposium on VLSI (GLSVLSI), Houston, Texas, USA, pp. 211–216, May 2014. (CCF-C) [DOI, PDF]
  24. Guangda Zhang, Wei Song, Jim Garside, Javier Navaridas, and Zhiying Wang. Transient fault tolerant QDI interconnects using redundant check code. In Proceedings of EUROMICRO Conference on Digital System Design (DSD), Santander, Spain, pp. 3–10, September 2013. [DOI, PDF]
  25. Wei Song, Doug Edwards, Jim Garside, and William J. Bainbridge. Area efficient asynchronous SDM routers using 2-stage Clos switches. In Proceedings of Design, Automation & Test in Europe (DATE), Dresden, Germany, pp. 1495–1500, March 2012. (CCF-B) [DOI, PDF, PPT]
  26. 宋威, Doug Edwards. 异步片上网络研究综述. 计算机辅助设计与图形学学报, 2012, 24(6): 699–709.
    (Wei Song and Doug Edwards. Survey of asynchronous networks-on-chip. Journal of Computer-Aided Design & Computer Graphics, vol. 24, no. 6, pp. 699–709, 2012) [DOI, PDF]
  27. Wei Song and Doug Edwards. Asynchronous spatial division multiplexing router. Microprocessors and Microsystems, vol. 35, no. 2, pp. 85–97, 2011. (CCF-C) [DOI, PDF]
  28. Wei Song, Doug Edwards, Zhenyu Liu, and Sohini Dasgupta. Routing of asynchronous Clos networks. IET Computers & Digital Techniques, vol. 5, no. 6, pp. 452–467, 2011. (CCF-C) [DOI, PDF]
  29. Wei Song and Doug Edwards. An asynchronous routing algorithm for Clos networks. In Proceedings of International Conference on Application of Concurrency to System Design (ACSD), Braga, Portugal, pp. 67–76, 2010. [DOI, PDF, PPT, MP3]
  30. Wei Song and Doug Edwards. A low latency wormhole router for asynchronous on-chip networks. In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, ROC, pp. 437–443, 2010. (CCF-C) [DOI, PDF, PPT, MP3]
  31. Wei Song and Doug Edwards. Building asynchronous routers with independent sub-channels. In Proceedings of International Symposium on SoC, Tampere, Finland, pp. 48–51, 2009. [DOI, PDF]
  32. Wei Song, Doug Edwards, Jose Luis Nunez-Yanez, and Sohini Dasgupta. Adaptive stochastic routing in fault-tolerant on-chip networks. In Proceedings of International Symposium on Networks-on-Chip (NoCS), San Diego, USA, pp. 32–37, 2009. (CCF-C) [DOI, PDF, PPT]

    33. FPGA, VLSI

  33. Wei Song, Dirk Koch, Mikel Lujan, and Jim Garside. Parallel hardware merge sorter. In Proceedings of International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington DC, United States, pp. 95–102, May 2016. (CCF-C) [DOI, PDF, PPT]
  34. Oriol Arcas Abella, Geoffrey Ndu, Nehir Sonmez, Mohsen Ghasempour, Adria Armejach, Javier Navaridas, Wei Song, John Mawer, Adrian Cristal, and Mikel Lujan. An empirical evaluation of high-level synthesis languages and tools for database acceleration. In Proceedings of International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, pps. 8, September 2014. (CCF-C) [DOI, PDF]
  35. 宋威, 方穗明, 姚丹, 张立超, 钱程. 多FPGA的时钟同步. 计算机工程, 2008, 34(7): 245–247.
    (Wei Song, Suiming Fang, Dan Yao, Lichao Zhang, and Cheng Qian. Clock synchronization in multi-FPGA designs. Computer Engineering, vol. 34, no. 7, pp. 245–247, 2008) [DOI, URL, PDF, PDF]
  36. 宋威, 方穗明. 基于BUFGMUX与 DCM的FPGA时钟电路设计. 现代电子技术, 2006, 29(2): 141–143.
    (Wei Song and Suiming Fang. Clock circuit design in FPGA based on BUFGMUX, and DCM. Modern Electronic Technique, vol. 29, no. 2, pp. 141–143, 2006) [DOI, URL, PDF]

    37. Electronic Design Automation, VLSI

  37. Wei Song, Jim Garside, and Doug Edwards. Automatic data path extraction in large-scale register-transfer level designs. In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, pp. 377–380, June 2014. (CCF-C) [DOI, PDF, PPT]
  38. Wei Song and Jim Garside. Automatic controller detection for large scale RTL designs. In Proceedings of EUROMICRO Conference on Digital System Design (DSD), Santander, Spain, pp. 884–851, September 2013 [DOI, PDF, PPT]

    39. CANopen, Embedded Systems

  39. 徐喆, 闫士珍, 宋威, 张卓. 基于MC9S12DP512和μC/OS-II的CANopen主站开发. 计算机工程与科学, 2009, 31(5): 118–120.
    (Zhe Xu, Shizhen Yan, Wei Song, and Zhuo Zhang. Development of the CANopen master based on MC9S12DP512 and μC/OS-II. Computer Engineering and Science, vol. 31, no. 5, pp. 118–120, 2009) [DOI, URL, PDF]
  40. 徐喆, 闫士珍, 宋威. 基于散列表的CANopen对象字典的设计. 计算机工程, 2009, 35(8): 44–46.
    (Zhe Xu, Shizhen Yan, and Wei Song. Object dictionary design of CANopen based on hash table. Computer Engineering, vol. 35, no. 8, pp. 44–46, 2009) [DOI, URL, PDF, PDF]
  41. 宋威, 方穗明, 张明杰, 徐喆. 任务调度在CANopen主站设计中的应用. 计算机测量与控制, 2008(16): 558–560.
    (Wei Song, Suiming Fang, Mingjie Zhang, and Zhe Xu. Task scheduler in the design of CANopen master. Computer Measurement & Control, vol. 16, no. 4, pp. 558–560, 2008) [URL, PDF]
  42. Wei Song, Shizhen Yan, Zhe Xu, and Suiming Fang. Transplantable CANopen master based on non-preemptive task scheduler. In Proceedings of International Conference on Automation and Logistics (ICAL), pp. 557–562, 2007. [DOI, PDF]

    43. Books

  43. Wei Song and Guangda Zhang. Asynchronous On-Chip Networks and Fault-Tolerant Techniques. CRC press, Boca Raton, FL, United States, ISBN: 9781032255750, April 2022. [DOI, Preview]

    44. Thesis and Dissertations

  44. Wei Song. Spatial parallelism in the routers of asynchronous on-chip networks. PhD Thesis, School of Computer Science, the University of Manchester, Manchester, UK, 2011. [PDF]
  45. 宋威. CANopen现场总线应用层协议主站的开发与实现. 工学硕士学位论文, 电子信息与控制工程学院, 北京工业大学, 北京, 中国, 2008.
    (Wei Song. The design and implementation of a master of the application layer of CANopen. Master Dissertation, School of Electronic Information and Control Engineering, Beijing University of Technology, Beijing, P.R.China, 2008 ) [PDF]
  46. 宋威. 802.11g无线网卡Baseband的FPGA验证和接口设计. 学士毕业论文, 电子信息与控制工程学院, 北京工业大学, 北京, 中国, 2005.
    (Wei Song. FPGA function verification and interface design for the baseband of IEEE 802.11g WLAN network card. Bachelor Dissertation, School of Electronic Information and Control Engineering, Beijing University of Technology, Beijing, P.R.China, 2005) [PDF]

    47. Patent

  47. 张光达, 宋威, 戴华东. 一种双轨信号异步传输链路系统. 中国发明专利, 申请号201911392277.2, 专利号CN111198838B, 2020. [PDF]
  48. 徐喆, 闫士珍, 宋威, 余春暄, 段建民, 张明杰. 一种实现CANopen主站的方法. 中国发明专利, 申请号200810056824.5, 专利号CN101222510B, 2010. [PDF]

Non-Refereed Papers

  • Wei Song, Rui Hou, Peng Liu, Xiaoxin Li, Peinan Li, Lutan Zhao, Xiaofei Fu, Yifei Sun, and Dan Meng. Remapped cache layout: Thwarting cache-based side-channel attacks with a hardware defense. arXiv:2211.06056, November 2022. [ArXiv]
  • Zhenzhen Li and Wei Song. 升级RISC-V的指令级仿真器Spike的缓存模型. In 中国RISC-V论坛, 中国深圳, 2019年11月13日. [PDF]
  • Wei Song, Rui Hou, and Dan Meng. Defeating the recent AnC attack by simply hashing the cache indexes — implemented in a BOOM SoC. In 8th RISC-V Workshop, Barcelona, Spain, May 2018. [PDF, POSTER]
  • Wei Song, Alex Bradbury, and Robert Mullins. Towards general purpose tagged memory. In 2nd RISC-V Workshop, Berkeley, CA, US, June 2015. [PDF]
  • Wei Song and Doug Edwards. Using Clos switches in area efficient asynchronous SDM routers. In Proceedings of the UK Electronics Forum, Manchester, UK, July 2011. [PDF]
  • Wei Song and Doug Edwards. Improving the throughput of asynchronous on-chip networks with SDM. In Proceedings of the UK Electronics Forum, Newcastle, UK, June 2010. [PDF, PPT, POSTER]
  • Wei Song and Doug Edwards. Channel Slicing: a way to build fast routers for asynchronous NoCs. In Proceedings of the UK Asynchronous Forum, Bristol, UK, September 2009. [PDF]
  • Wei Song and Doug Edwards. A dynamic link allocation router. In Proceedings of the UK Asynchronous Forum, Manchester, UK, September 2008. [PDF]
  • 宋威. C语言实现MATLAB 6.5中M文件的方法. 计算机与信息技术, 2004, 7(12): 57–58.
    (Wei Song. The method of using m-files of MATLAB6.5 in C language. Computer and Information Technology, Vol. 7, No. 12, pp. 57–58, 2004) [PDF]

Presentations

  • 支持多核并行访问的高性能标签缓存设计. 邀请报告, RISC-V系统软件及软硬协同技术专刊论坛, 中国软件大会, 中国西安, 2023年11月15日. [PPT]
  • 可抵御缓存侧信道攻击的随机化缓存设计. RISC-V中国峰会, 中国上海, 2024年8月23日. [PPT]
  • 可抵御缓存侧信道攻击的随机化缓存设计. 邀请报告, RISC-V技术及生态研讨会, 中国科学院软件研究所, 中国北京, 2023年8月22日. [PPT]
  • 自我体会之创新的难度. 中国科学院大学网安学院, 中国北京, 2023年5月16日. [PPT]
  • 计算机体系结构与安全. 中国科学院大学网安学院, 中国北京, 2021年10月23日. [PPT]
  • Randomized last level caches are still vulnerable to cache side channel attacks! But we can fix it. IEEE Symposium on Security and Privacy (S&P), Online, 25 May 2021. [PPT, Talk Preview, Video]
  • RISC-V与处理器设计. 苏黎世-中国科学俱乐部, 线上, 2021年1月23日. [PPT]
  • 支持一致性缓存的Spike仿真器. CRVA联盟技术研讨会, 中国北京, 2020年7月18日. [PPT, Video]
  • Dynamically finding minimal eviction sets can be quicker than you think for side-channel attacks against the LLC. 邀请报告, 中国科学院信息工程研究所第四研究室研究生讨论班, 中国北京, 2019年10月19日. [PPT]
  • Dynamically finding minimal eviction sets can be quicker than you think for side-channel attacks against the LLC. International Symposium on Research in Attacks, Intrusions and Defenses (RAID), Beijing, China, 25 September 2019. [PPT]
  • Extending Rocket-Chip with Verilog peripheral IPs. 邀请报告, SiFive RISC-V/Chisel线下交流会, SiFive, 中国上海, 2018年9月8日. [PPT]
  • 浅谈RISC-V指令集. 邀请报告, RISC-V开放指令集和软硬件生态, 中国计算机协会第二十二届工程与工艺学术年会暨第八届“微处理器技术”论坛, 中国银川, 2018年8月16日. [PPT]
  • 浅谈RISC-V指令集. 邀请报告, RISC-V开源芯片线上讨论, 中国科学院计算所，中国北京，2018年6月22日. [PPT]
  • lowRISC多核开源平台和RISC-V在中国的发展. 邀请报告, RISC-V技术进展及产业生态研讨, 中国电子信息产业发展研究院，中国北京，2018年4月25日. [PPT]
  • lowRISC: An opensourced SoC provider based on RISC-V Rocket cores. Invited talk, Micro Processor Research and Development Center of Peking University, Beijing, China, 2 June 2017.
  • lowRISC: An opensourced SoC provider based on RISC-V Rocket cores. Invited talk, Institute of Computing Technology Chinese Academy of Science, Beijing, China, 31 May 2017. [PPT]
  • The 4th lowRISC release: tagged memory and minion cores. 6th RISC-V Workshop, Shanghai, China, 10 May 2017. [PPT, Video]
  • Trace debugging in lowRISC. 4th RISC-V Workshop, Boston MA, US, 12 July 2016. [PPT, Video]
  • Parallel hardware merge sorter. International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington DC, US, 2 May 2016. [PPT]
  • Untethering the RISC-V Rocket chip. 3rd RISC-V Workshop, Redwood, CA, US, 6 January 2016. [PPT, Video]
  • Untethering the Rocket-chip, Computer architecture group scrum talk, Cambridge, UK, 7 October 2015. [PPT]
  • Untethered lowRISC, memory mapped IO and TileLink/AXI, lowRISC meeting, Cambridge, UK, 27 July 2015. [PPT]
  • Towards general purpose tagged Memory. 2nd RISC-V Workshop, Berkeley, CA, US, 30 June 2015. [PPT, Video]
  • Automatic data path extraction in large-scale register-transfer level designs, IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, 2 June 2014. [PPT]
  • High-throughput sorting by dynamically merging multiple hardware sequential sorters, APT Group presentation, University of Manchester, Manchester, UK, 3 April 2014. [PPT]
  • Utilizing signal-level data flow graph in analysing large-scale RTL circuits, APT Group presentation, University of Manchester, Manchester, UK, 12 March 2014. [PPT]
  • Automatic controller detection for large scale RTL designs. EUROMICRO Conference on Digital System Design (DSD), Santander, Spain, 6 September 2013 [PPT]
  • GAELS project meeting: automatic data path extraction, GAELS project meeting, Newcastle University, Newcastle upon Tyne, UK, 15 November 2013. [PPT]
  • GAELS progress, GAELS project meeting, University of Manchester, Manchester, UK, 13 March 2013. [PPT]
  • GAELS progress, GAELS project meeting, Newcastle University, Newcastle upon Tyne, UK, 31 August 2012. [PPT]
  • GAELS project progress, GAELS project meeting, University of Manchester, Manchester, UK, 19 April 2012. [PPT]
  • Area efficient asynchronous SDM routers using 2-stage Clos switches. Design, Automation & Test in Europe (DATE), Dresden, Germany, 15 March 2012. [PPT]
  • Asynchronous Verilog --- interface between behavioural and pipeline synthesis, GAELS project meeting, Newcastle University, Newcastle upon Tyne, UK, 22 November 2011. [PPT]
  • Using Clos switches in area efficient asynchronous SDM routers. UK Electronics Forum, Manchester, UK, 4 July 2011. [PPT]
  • Using Clos switches in area efficient asynchronous SDM routers. Invited talk, Newcastle University, Newcastle upon Tyne, UK, 9 March 2011. [PPT]
  • Improving the throughput of asynchronous on-chip networks with SDM. UK Electronics Forum, Newcastle, UK, June 2010. [PPT]
  • An asynchronous routing algorithm for Clos networks. International Conference on Application of Concurrency to System Design (ACSD), Braga, Portugal, 23 June 2010. [PPT, MP3]
  • My trip towards the PhD, Invited talk, course COMP7000, School of Computer Science, University of Manchester, Manchester, UK, 12 November 2010. [PPT]
  • Asynchronous SDM router, NoRC project meeting, University of Manchester, Manchester, UK, 9 April 2010. [PPT]
  • A low latency wormhole router for asynchronous on-chip networks. Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, ROC, 20 January 2010. [PPT, MP3]
  • From channel slicing to spatial division multiplexing --- the asynchronous NoC router design, APT Group presentation, University of Manchester, Manchester, UK, 3 December 2009. [PPT]
  • How to design fast asynchronous routers for asynchronous on-chip networks, Research student symposium, School of Computer Science, University of Manchester, Manchester, UK, October 2009. [PPT]
  • From channel slicing to spatial division multiplex for asynchronous networks-on-chip, PhD second year review, University of Manchester, Manchester, UK, September 2009. [PPT]
  • Channel slicing: a way to build fast routers for asynchronous NoCs. UK Asynchronous Forum, Bristol, UK, 15 September 2009. [PPT]
  • A wormhole router design, NoRC project meeting, Bristol University, Bristol, UK, 30 July 2009. [PPT]
  • NoRC project meeting report, NoRC project meeting, University of Manchester, Manchester, UK, 23 March 2009. [PPT]
  • The simulation of the dynamic link allocation router (DyLAR), NoRC project meeting, Bristol University, Bristol, UK, 28 October 2008. [PPT]
  • A dynamic link allocation router. UK Asynchronous Forum, Manchester, UK, 9 September 2008. [PPT]
  • A dynamic link allocation router (DyLAR) for asynchronous network-on-chips, APT Group presentation, University of Manchester, Manchester, UK, 21 August 2008. [PPT]
  • CANopen现场总线应用层协议主站的开发与实现. 工学硕士学位论文, 电子信息与控制工程学院, 北京工业大学, 北京, 中国, 2008. [PPT]
  • Router for NoRC, NoRC project meeting, University of Manchester, Manchester, UK, May 2008. [PPT]