Wei Song's web space

09/2026 to present
Professor
School of Computer and Communication Engineering, University of Science and Technology Beijing, P.R.China
  • Enhance system security with new processor and cache micro-architectures. (09/2026 to present)
11/2017 to 08/2026
Professor
Institute of Information Engineering, Chinese Academy of Sciences, P.R.China
  • Professor (10/2025), Associate Professor (11/2017 to 09/2025); supervisor of Master (09/2018) and PhD (09/2019) students; receiver of the CAS Pioneer Hundred Talents Program.
  • Enhance system security with new processor and cache micro-architectures. (11/2017 to 08/2026)
  • Open hardware designs for computer architecture research. (10/2018 to 08/2026)
    • A fast cache model for cache side-channel attack/defense researches [JOS'25, RAID'19].
    • Improving the usefulness of open sourced processors [CSA'21].
11/2014 to 10/2017
Research Associate
The Computer Laboratory, University of Cambridge, UK
  • LowRISC: An open-source System-on-Chip (SoC) hardware platform using the 64-bit RISC-V instruction. (11/2014 to 10/2017)
    • Lead hardware designer for the lowRISC code release fron version 0.1 to 0.4.
    • Added tagged memory into the Rocket-chip to enhance system security using metadata processing.
    • Helped the integration of trace debugger on lowRISC SoC.
    • Produced the fist untethered Rocket-chip which can boot Linux independently from SD.
10/2011 to 10/2014
Research Associate
School of Computer Science, the University of Manchester, UK
  • EPSRC project EP/L000563/1: "Continuous on-line adaptation in many-core systems: From graceful degradation to graceful amelioration." (08/2014 to 10/2014)
    • Investigate the intra/inter-chip task (neuron) migration in the SpiNNaker system.
  • EPSRC project EP/I038306/1: "Globally asynchronous elastic logic synthesis." (10/2011 to 09/2014)
    • Implemented a RTL Verilog HDL parser using Bison and Flex.
    • Signal-level data flow graph.
    • Automatic finite state machine (FSM) detection [DSD'13].
    • Automatic data-path extraction [ISCAS'14].
    • Automatic interface type recognition.
    • A muti-dimensional range calculation library: cppRange
  • Fault-tolerance techniques for asynchronous on-chip networks. (09/2012 to 09/2014)
    • Redundent code for QDI 1-of-N pipeline to avoid errors caused by 1-bit transient fault [DSD'13, Micpro'14].
    • Detect and recover from the deadlock caused by permanent faults in asynchronous SDM routers [GLSVLSI'14, ASYNC'14].
  • Large-scale sorter on FPGA for database applications. (09/2013 to 10/2016)
    • Parallel merge sorter to break the throughput limit of sequential sorters.
09/2007 to 09/2011
PhD student
School of Computer Science, the University of Manchester, UK
  • Thesis: Spatial parallelism in the routers of asynchronous on-chip networks
  • Scholarship and grants:
    • EPSRC Doctoral Training Award EP/P503833/1 (10/2007 to 3/2011)
    • EPSRC Project Grant EP/E06065X/1 (4/2008 to 7/2011): Energy efficient networks-on-chip for dynamically reconfigurable computing platforms
    • Bursary of the School of Computer Science, University of Manchester (10/2007--3/2011)
  • Design of asynchronous routers for on-chip networks.
    • Designed and implemented asynchronous spatial division multiplexing (SDM) routers for asynchronous on-chip networks [Micpro'11, DATE'12].
    • Designed and implemented a high-speed asynchronous wormhole router for asynchronous on-chip networks [ISSOC'09, ASPDAC'10].
    • Designed and implemented the first asynchronous scheduler for three-stage S3 Clos networks [ACSD'10, IETCDT'11].
    • All designs are coded in synthesizable Verilog HDL (Faraday 130nm cell library), implemented by Synopsys DC-Topo, ICC, StarXRC, PrimeTime-PX, and simulated by SystemC/Verilog co-simulation using Cadence NC-Sim.
  • Adaptive stochastic routing in fault-tolerant on-chip networks [NOCS'09].
09/2005 to 09/2008
Master student
School of Electronic Information and Control Engineering, Beijing University of Technology, P.R.China
  • M.S.EE. in Automation
  • Designed and implemented an ANSI C non-preemptive real-time scheduler for the central controller of electrical vehicles. (supported by Beijing Sci. Foundation \#KZ20041000501).
10/2004 to 11/2006
Research Assistant
Beijing Embedded System Key Lab, Beijing University of Technology, P.R.China
  • Implementing the ASIC prototypes into FPGA verification platforms for the final hardware test before tape out. FPGA platforms include Xilinx Virtex-4 and II. ASIC prototypes include the baseband for ATSC, DVB-T, DVB-C and WLAN 802.11g.
09/2001 to 09/2005
Undergraduate student
School of Electronic Information and Control Engineering, Beijing University of Technology, P.R.China
  • B.S.EE. in Automation
  • Minor in Computer Science
09/1989 to 07/2001
The High School Affiliated to Renmin University of China, Beijing, P.R.China
No.1 Middle School Attached To Central China Normal University, Wuhan, P.R.China
The Prime School Attached To Central China Normal University, Wuhan, P.R.China