- Thwart cache-based side-channel attacks using randomized caches.
- Randomized last level caches are still vulnerable to cache side channel attacks! But we can fix it published at S&P 2021.
- Dynamically finding minimal eviction sets can be quicker than you think for side-channel attacks against the LLC published in RAID 2019.
- Poster in RISC-V workshop, May 2018
- Presentation at RISC-V Shanghai Day, 2018
- Using hardware implemented tagged memory to protect systems from control-flow hijacking attacks.
System security benchmark
- Produce a benchmark to test the security safety of a system (inclusing OS, compiler and hardware).
High throughput sorting
- Sorting is a data-depenedent and bandwidth consuming algorithm. Based on the recently proposed hardware parallem merge-tree sorter, this project tries to produce a demo system that utilizing this hardware sorter to dramastically accelerte sorting in software.
- A paper published in FCCM 2016
lowRISC open-source SoC
- The lowRISC platform aims to be the "Linux of the hardware world", providing a high quality, secure, and open base for derivative designs. We will prove our design with volume silicon manufacture and an accompanying low-cost development board. Our goal is to lower the barrier of entry to producing custom silicon, establishing a vibrant ecosystem around secure and open hardware designs. lowRISC was formed as a not-for-profit community-driven organisation to pursue these aims.
Asynchronous Verilog Synthesiser
- Generate elastic or asynchronous circuits from synchronous RTL designs written in Verilog HDL.
- A C++ library for parsing SAIF (Switching Activity Interchange Format) files.
- A C++ library for interoperability between C++ and Tcl.
- Adopted from the original C++/Tcl designed by Maciej Sobczak.
- 中文文档(Chinese Document)
- A standalone C++ preprocessor for the Verilog HDL language.
- Adopted from the Verilog Perl tool suite designed by Wilson Snyder.
Asynchronous Spatial Division Multiplexing (SDM) Router
- Hardware designs of asynchronous SDM routers using Nangate 45nm cell library. Gate-level, synthesisable netlist written in Verilog HDL. SystemC testbenches and synthesis scripts for Synopsys DC provided.