English|中文

2025年我还剩0个博士招生指标(保送直博、普博或硕转博)，可能还有1个硕士指标。
如果对我的研究方向感兴趣，请务必提前用Email联系我，仅在复试填报志愿时报我不会被录取。
For international students, I am NOT in a position to supervise international students even with a full scholarship!

Welcome to my personal website!

I am Wei Song, an Associate Professor at the the Institute of Information Engineering, CAS. I was awarded PhD in computer science in 2011 from the School of Computer Science at the University of Manchester. Between 2011 and 2017, I was a Research Associate working for the University of Manchester and the University of Cambridge, where I researched the EDA for asynchronous circuits and the design of multicore processors. I was a core member of the lowRISC open SoC project and led the first four SoC releases. My current research interests include compiler optimization for processor and OS security, secure computer architecture, secure cache hierarchy, design of RISC-V processors, etc.

Some of my highlights in research and life:

• Designed a parallel tag cache for hardware managed tagged memory in multicore processors (TC 2024).
• Implemented the first processor (a Rocket-Chip) defensed by LLC randomization (TC 2024).
• Proposed a new eviction set search algorithm (CTPP) which is the fast on Intel processors in 2023 (RAID 2023).
• Proposed to detect cache side-channel attacks by observing the distribution of cache evictions on cache sets (IEEE S&P 2021).
• Verified that the timing assumption on attacks described in the randomized CEASER cache is wrong.
• Designed a high-speed cache simulation model supporting cache coherence.
• Co-founder of the grass-rooted RISC-V group in China: CNRV.
• Led the the hardware design of the first four releases of lowRISC SoC.
• Designed the fastest FPGA merge sorter in the world at 2016 (FCCM 2016).
• Became a Research Associate at the University of Cambridge.
• Jointly designed the first QDI NoC tolerant to permanent faults.
• Designed the first SDM QDI NoC.
• Full PhD scholarship from the UK EPSRC.

欢迎来到我的个人主页 ;-)

我是宋威，中国科学院信息工程研究所，副研究员，博士生导师，中国科学院率先行动百人计划C类入选者。我于2011年获得英国曼彻斯特大学计算机博士学位，2011年至2017年在曼彻斯特大学计算机学院和剑桥大学计算机学院工作，研究异步电路的EDA工具设计和多核处理器设计，曾经是剑桥大学开源片上多核SoC项目（lowRISC）的硬件负责人，主持了其前4版的SoC硬件开发。现在我的主要研究方向包括：针对处理器和系统安全的编译器优化、安全处理器架构、安全高速缓存架构、基于RISC-V的安全处理器设计等等。

我研究和生活经历中的主要闪光点：

• 实现了一个支持多核高速并行访问的标签缓存 (TC 2024)。
• 实现了第一个支持末级缓存随机化防御的处理器(Rocket-Chip, TC 2024)。
• 提出了一种可在Intel处理器上迅速构造缓存驱逐集的算法CTPP(2023年最快, RAID 2023)。
• 提出了一种利用驱逐事件在缓存组上的分布来检测缓存侧信道攻击的新方法(IEEE S&P 2021)。
• 证明了随机化缓存防御方案CEASER关于攻击的时间分析是错误的。
• 实现了一个高速的一致性缓存仿真模型。
• 合作建立了中国RISC-V草根小组CNRV。
• 主持开发了lowRISC开源SoC的前4版实现。
• 实现了2016年最快的FPGA归并排序器(FCCM 2016)。
• 到剑桥大学计算机实验室当博士后副研究员。
• 合作完成了第一个能抵御永久性错误的QDI片上异步网络。
• 完成了第一个空分复用的QDI异步片上网络。
• 获得英国EPSRC全奖到曼彻斯特大学计算机学院读博士。