Wei Song's web space


    Journal and Conference Papers


    Asynchronous Network-on-Chip, VLSI

  1. Guangda Zhang, Jim Garside, Wei Song, Javier Navaridas and Zhiying Wang. Deadlock recovery in asynchronous networks on chip in the presence of transient faults. In Proc. of International Symposium on Asynchronous Circuits and Systems (ASYNC), Silicon Valley, California, US, pp. 100–107, May 2015. [DOI, PDF]
  2. Guangda Zhang, Wei Song, Jim Garside, Javier Navaridas and Zhiying Wang. Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes. Microprocessors and Microsystems, vol. 38, no. 8, pp. 826–842, 2014. [DOI, PDF]
  3. Guangda Zhang, Wei Song, Jim Garside, Javier Navaridas and Zhiying Wang. An asynchronous SDM network-on-chip tolerating permanent faults. In Proc. of International Symposium on Asynchronous Circuits and Systems (ASYNC), Potsdam, Germany, pp. 9–16, May 2014. [DOI, PDF]
  4. Wei Song, Guangda Zhang and Jim Garside. On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip. In Proc. of International Conference of the Great Lakes Symposium on VLSI (GLSVLSI), Houston, Texas, USA, pp. 211–216, May 2014. [DOI, PDF]
  5. Guangda Zhang, Wei Song, Jim Garside, Javier Navaridas and Zhiying Wang. Transient fault tolerant QDI interconnects using redundant check code. In Proc. of EUROMICRO Conference on Digital System Design (DSD), Santander, Spain, pp. 3–10, September 2013. [DOI, PDF]
  6. Wei Song, Doug Edwards, Jim Garside and William J. Bainbridge. Area efficient asynchronous SDM routers using 2-stage Clos switches. In Proc. of Design, Automation & Test in Europe (DATE), Dresden, Germany, pp. 1495–1500, March 2012. [DOI, PDF, PPT]
  7. 宋威, Doug Edwards. 异步片上网络研究综述. 计算机辅助设计与图形学学报, 2012, 24(6): 699–709.
    (Wei Song and Doug Edwards. Survey of asynchronous networks-on-chip. Journal of Computer-Aided Design & Computer Graphics, vol. 24, no. 6, pp. 699–709, 2012) [DOI, PDF]
  8. Wei Song and Doug Edwards. Asynchronous spatial division multiplexing router. Microprocessors and Microsystems, vol. 35, no. 2, pp. 85–97, 2011. [DOI, PDF]
  9. Wei Song, Doug Edwards, Zhenyu Liu and Sohini Dasgupta. Routing of asynchronous Clos networks. IET Computers & Digital Techniques, vol. 5, no. 6, pp. 452–467, 2011. [DOI, PDF]
  10. Wei Song and Doug Edwards. An asynchronous routing algorithm for Clos networks. In Proc. of International Conference on Application of Concurrency to System Design (ACSD), Braga, Portugal, pp. 67–76, 2010. [DOI, PDF, PPT, MP3]
  11. Wei Song and Doug Edwards. A low latency wormhole router for asynchronous on-chip networks. In Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, ROC, pp. 437–443, 2010. [DOI, PDF, PPT, MP3]
  12. Wei Song and Doug Edwards. Building asynchronous routers with independent sub-channels. In Proc. of International Symposium on SoC, Tampere, Finland, pp. 48–51, 2009. [DOI, PDF]
  13. Wei Song, Doug Edwards, Jose Luis Nunez-Yanez, and Sohini Dasgupta. Adaptive stochastic routing in fault-tolerant on-chip networks. In Proc. of International Symposium on Networks-on-Chip (NoCS), San Diego, USA, pp. 32–37, 2009. [DOI, PDF, PPT]

  14. FPGA, VLSI

  15. Wei Song, Dirk Koch, Mikel Lujan and Jim Garside. Parallel hardware merge sorter. In Proc. of International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington DC, United States, pp. 95–102, May 2016. [DOI, PDF, PPT]
  16. Oriol Arcas Abella, Geoffrey Ndu, Nehir Sonmez, Mohsen Ghasempour, Adria Armejach, Javier Navaridas, Wei Song, John Mawer, Adrian Cristal, and Mikel Lujan. An empirical evaluation of high-level synthesis languages and tools for database acceleration. In Proc. of International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, pps. 8, September 2014. [DOI, PDF]
  17. 宋威, 方穗明, 姚丹, 张立超, 钱程. 多FPGA的时钟同步. 计算机工程, 2008, 34(7): 245–247.
    (Wei Song, Suiming Fang, Dan Yao, Lichao Zhang, and Cheng Qian. Clock synchronization in multi-FPGA designs. Computer Engineering, vol. 34, no. 7, pp. 245–247, 2008) [DOI, URL, PDF, PDF]
  18. 宋威, 方穗明. 基于BUFGMUX与 DCM的FPGA时钟电路设计. 现代电子技术, 2006, 29(2): 141–143.
    (Wei Song and Suiming Fang. Clock circuit design in FPGA based on BUFGMUX and DCM. Modern Electronic Technique, vol. 29, no. 2, pp. 141–143, 2006) [DOI, URL, PDF]

  19. Electronic Design Automation, VLSI

  20. Wei Song, Jim Garside and Doug Edwards. Automatic data path extraction in large-scale register-transfer level designs. In Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, pp. 377–380, June 2014. [DOI, PDF, PPT]
  21. Wei Song and Jim Garside. Automatic controller detection for large scale RTL designs. In Proc. of EUROMICRO Conference on Digital System Design (DSD), Santander, Spain, pp. 884–851, September 2013 [DOI, PDF, PPT]

  22. CANopen, Embedded Systems

  23. 徐喆, 闫士珍, 宋威, 张卓. 基于MC9S12DP512和μC/OS-II的CANopen主站开发. 计算机工程与科学, 2009, 31(5): 118–120.
    (Zhe Xu, Shizhen Yan, Wei Song, and Zhuo Zhang. Development of the CANopen master based on MC9S12DP512 and μC/OS-II. Computer Engineering and Science, vol. 31, no. 5, pp. 118–120, 2009) [DOI, URL, PDF]
  24. 徐喆, 闫士珍, 宋威. 基于散列表的CANopen对象字典的设计. 计算机工程, 2009, 35(8): 44–46.
    (Zhe Xu, Shizhen Yan, and Wei Song. Object dictionary design of CANopen based on hash table. Computer Engineering, vol. 35, no. 8, pp. 44–46, 2009) [DOI, URL, PDF, PDF]
  25. 宋威, 方穗明, 张明杰, 徐喆. 任务调度在CANopen主站设计中的应用. 计算机测量与控制, 2008(16): 558–560.
    (Wei Song, Suiming Fang, Mingjie Zhang, and Zhe Xu. Task scheduler in the design of CANopen master. Computer Measurement & Control, vol. 16, no. 4, pp. 558–560, 2008) [URL, PDF]
  26. Wei Song, Shizhen Yan, Zhe Xu, and Suiming Fang. Transplantable CANopen master based on non-preemptive task scheduler. In Proc. of International Conference on Automation and Logistics (ICAL), pp. 557–562, 2007. [DOI, PDF]

Thesis and Dissertations

  • Wei Song. Spatial Parallelism in the Routers of Asynchronous On-Chip Networks. PhD Thesis, School of Computer Science, the University of Manchester, Manchester, UK, 2011. [PDF]
  • 宋威. CANopen现场总线应用层协议主站的开发与实现. 工学硕士学位论文, 电子信息与控制工程学院, 北京工业大学, 北京, 中国, 2008.
    (Wei Song. The design and implementation of a master of the application layer of CANopen. Master Dissertation, School of Electronic Information and Control Engineering, Beijing University of Technology, Beijing, P.R.China, 2008 ) [PDF]
  • 宋威. 802.11g无线网卡Baseband的FPGA验证和接口设计. 学士毕业论文, 电子信息与控制工程学院, 北京工业大学, 北京, 中国, 2005.
    (Wei Song. FPGA function verification and interface design for the baseband of IEEE 802.11g WLAN network card. Bachelor Dissertation, School of Electronic Information and Control Engineering, Beijing University of Technology, Beijing, P.R.China, 2005) [PDF]

Patent

  • 徐喆, 闫士珍, 宋威, 余春暄, 段建民, 张明杰. 一种实现CANopen主站的方法. 中国发明专利, 申请号200810056824.5, 专利号CN101222510B, 2010.
    (Zhe Xu, Shizhen Yan,Wei Song, Chunxuan Yu, Jianmin Duan, and Mingjie Zhang. A method to implement the CANopen master. Chinese invention patent, App. No. CN200810056824.5, Grant No. CN101222510B, 2010) [URL]

Non-refereed Papers

  • Wei Song, Alex Bradbury and Robert Mullins. Towards General Purpose Tagged Memory. In 2nd RISC-V Workshop, Berkeley, CA, US, June 2015. [PDF]
  • Wei Song and Doug Edwards. Using Clos switches in area efficient asynchronous SDM routers. In Proc. of the UK Electronics Forum, Manchester, UK, July 2011. [PDF]
  • Wei Song and Doug Edwards. Improving the throughput of asynchronous on-chip networks with SDM. In Proc. of the UK Electronics Forum, Newcastle, UK, June 2010. [PDF, PPT, POSTER]
  • Wei Song and Doug Edwards. Channel Slicing: a way to build fast routers for asynchronous NoCs. In Proc. of the UK Asynchronous Forum, Bristol, UK, September 2009. [PDF]
  • Wei Song and Doug Edwards. A dynamic link allocation router. In Proc. of the UK Asynchronous Forum, Manchester, UK, September 2008. [PDF]
  • 宋威. C语言实现MATLAB 6.5中M文件的方法. 计算机与信息技术, 2004, 7(12): 57–58.
    (Wei Song. The method of using m-files of MATLAB6.5 in C language. Computer and Information Technology, Vol. 7, No. 12, pp. 57–58, 2004) [PDF]

Presentations

  • lowRISC: An opensourced SoC provider based on RISC-V Rocket cores. Invited talk, Institute of Computing Technology Chinese Academy of Science, Beijing, China, 31 May 2017. [PPT]
  • The 4th lowRISC release: tagged memory and minion cores. 6th RISC-V Workshop, Shanghai, China, 10 May 2017. [PPT, Video]
  • Trace debugging in lowRISC. 4th RISC-V Workshop, Boston MA, US, 12 July 2016. [PPT, Video]
  • Parallel hardware merge sorter. International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington DC, US, 2 May 2016. [PPT]
  • Untethering the RISC-V Rocket chip. 3rd RISC-V Workshop, Redwood, CA, US, 6 January 2016. [PPT, Video]
  • Untethering the Rocket-chip, Computer architecture group scrum talk, Cambridge, UK, 7 October 2015. [PPT]
  • Untethered lowRISC, memory mapped IO and TileLink/AXI, lowRISC meeting, Cambridge, UK, 27 July 2015. [PPT]
  • Towards general purpose tagged Memory. 2nd RISC-V Workshop, Berkeley, CA, US, 30 June 2015. [PPT, Video]
  • Automatic data path extraction in large-scale register-transfer level designs, IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, 2 June 2014. [PPT]
  • High-throughput sorting by dynamically merging multiple hardware sequential sorters, APT Group presentation, University of Manchester, Manchester, UK, 3 April 2014. [PPT]
  • Utilizing signal-level data flow graph in analysing large-scale RTL circuits, APT Group presentation, University of Manchester, Manchester, UK, 12 March 2014. [PPT]
  • Automatic controller detection for large scale RTL designs. EUROMICRO Conference on Digital System Design (DSD), Santander, Spain, 6 September 2013 [PPT]
  • GAELS project meeting: automatic data path extraction, GAELS project meeting, Newcastle University, Newcastle upon Tyne, UK, 15 November 2013. [PPT]
  • GAELS progress, GAELS project meeting, University of Manchester, Manchester, UK, 13 March 2013. [PPT]
  • GAELS progress, GAELS project meeting, Newcastle University, Newcastle upon Tyne, UK, 31 August 2012. [PPT]
  • GAELS project progress, GAELS project meeting, University of Manchester, Manchester, UK, 19 April 2012. [PPT]
  • Area efficient asynchronous SDM routers using 2-stage Clos switches. Design, Automation & Test in Europe (DATE), Dresden, Germany, 15 March 2012. [PPT]
  • Asynchronous Verilog --- interface between behavioural and pipeline synthesis, GAELS project meeting, Newcastle University, Newcastle upon Tyne, UK, 22 November 2011. [PPT]
  • Using Clos switches in area efficient asynchronous SDM routers. UK Electronics Forum, Manchester, UK, 4 July 2011. [PPT]
  • Using Clos switches in area efficient asynchronous SDM routers. Invited talk, Newcastle University, Newcastle upon Tyne, UK, 9 March 2011. [PPT]
  • Improving the throughput of asynchronous on-chip networks with SDM. UK Electronics Forum, Newcastle, UK, June 2010. [PPT]
  • An asynchronous routing algorithm for Clos networks. International Conference on Application of Concurrency to System Design (ACSD), Braga, Portugal, 23 June 2010. [PPT, MP3]
  • My trip towards the PhD, Invited talk, course COMP7000, School of Computer Science, University of Manchester, Manchester, UK, 12 November 2010. [PPT]
  • Asynchronous SDM router, NoRC project meeting, University of Manchester, Manchester, UK, 9 April 2010. [PPT]
  • A low latency wormhole router for asynchronous on-chip networks. Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, ROC, 20 January 2010. [PPT, MP3]
  • From channel slicing to spatial division multiplexing --- the asynchronous NoC router design, APT Group presentation, University of Manchester, Manchester, UK, 3 December 2009. [PPT]
  • How to design fast asynchronous routers for asynchronous on-chip networks, Research student symposium, School of Computer Science, University of Manchester, Manchester, UK, October 2009. [PPT]
  • From channel slicing to spatial division multiplex for asynchronous networks-on-chip, PhD second year review, University of Manchester, Manchester, UK, September 2009. [PPT]
  • Channel slicing: a way to build fast routers for asynchronous NoCs. UK Asynchronous Forum, Bristol, UK, 15 September 2009. [PPT]
  • A wormhole router design, NoRC project meeting, Bristol University, Bristol, UK, 30 July 2009. [PPT]
  • NoRC project meeting report, NoRC project meeting, University of Manchester, Manchester, UK, 23 March 2009. [PPT]
  • The simulation of the dynamic link allocation router (DyLAR), NoRC project meeting, Bristol University, Bristol, UK, 28 October 2008. [PPT]
  • A dynamic link allocation router. UK Asynchronous Forum, Manchester, UK, 9 September 2008. [PPT]
  • A dynamic link allocation router (DyLAR) for asynchronous network-on-chips, APT Group presentation, University of Manchester, Manchester, UK, 21 August 2008. [PPT]
  • CANopen现场总线应用层协议主站的开发与实现. 工学硕士学位论文, 电子信息与控制工程学院, 北京工业大学, 北京, 中国, 2008.
    ( The design and implementation of a master of the application layer of CANopen. Defence for Master degree, Beijing University of Technology, Beijing, P.R.China, 29 May 2008 ) [PPT]
  • Router for NoRC, NoRC project meeting, University of Manchester, Manchester, UK, May 2008. [PPT]