Wei Song's web space

Asynchronous Verilog Synthesiser

cppSaif

C++/Tcl

VPreproc

Asynchronous Spatial Division Multiplexing (SDM) Router

  • Hardware designs of asynchronous SDM routers using Nangate 45nm cell library. Gate-level, synthesisable netlist written in Verilog HDL. SystemC testbenches and synthesis scripts for Synopsys DC provided.
  • opencores.org/project,async_sdm_noc